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1 mx93011a mx93011a content 1.0 features 1.1 difference between mx93011 and mx93011a 2.0 function block diagram 3.0 pin configuration 3.1 pin descriptions 3.2 pin type summary 3.3 multiplex pins 4.0 function descrition 4.1 loop 4.2 modular addressing 4.3 auxiliary registers 4.4 stack 4.5 hold 4.6 memory maps 4.7 clock/timer/power down 4.8 addressing modes 4.9 interrupt 5.0 registers summary 6.0 registers description 7.0 instruction set summary 8.0 instruction set description 9.0 dc characterisics 10.0 ac timing and characterisics 11.0 order information 12.0 package information
p/n: pm0402 2 rev. 1.0 , jul 5, 1996 mx93011a mx93011a ? 16-bit, 46.5ns instruction cycle, up to 21mips dsp controller for dam (digital answering machine) ap- plication. ? 32-bit alu and 16-bit auxiliary alu (arau) work in parallel. ? 8 auxiliary registers for indirect addressing work with arau. ? 32-level hardware stack and nestable interrupt sup- port. ? 32-bit barrel shifter. ? 8-instruction looped up to 128 times capability. ? 64k words program rom space, 32k words may be internal. ? external rom option may replace internal 32k for fast prototyping. 1.0 features 1.1 difference between mx93011 and mx93011a 1. external memory wait state: i/o register(8) mx93011 76543210 01111111 mmsize sramwait mmwait romwait mx93011a 10 9 8 76543210 01111111111 mmsize sramwait mmwait romwait 2.stack register: mx93011:16x16 mx93011a:32x16 stack pointer register: mx93011 3210 0000 mx93011a 43210 00000 3.internal rom: mx93011 18kx16 mx93011a 32kx16 4.single low x' tal mode: in mx93011a, high x' tal is no longer needed. high clock(32.256 mhz) required for dsp running with can be generated from fll (frequence locked loop) by enabling fllen\ pin. x1 and x2 of high x'tal should be connected to vdd and gnd respectively in this mode. ? 64k words sram space, 2048 words internal. ? 32 internal io address. ? 1 independent interrupt pin, 1 nmi pin. ? 8 input pins. ? 8 bi-direction i/o pins. ? 19 output pins. ? hold or slow system clock for power management. ? 1/1024 sec or1 ms system tick timer for system timing. ? one codec interface. ? built-in dram controller;1g addressing space, with 1/4/8/16 data bit interface support. ? 0.6u single 5v supply, 100 pins pqfp
3 mx93011a mx93011a 2.0 function block diagram clock generator & fll dsp program control i/o ports program address unit 32x16 stack i/o mapped register 32kx16 program rom decode unit data ram address unit 1kx16 ram 1kx16 ram 16x16 mutiplier accumulator(32) +15/-15 shifter alu(32) memory interface dram interface codec interface ewr\ erd\ edce\ epce\ erom ed(15:0) ead(15:0) dwr\ drd\ cas\ ras\ cfs cmck cdx0 cdr0 program & data audio dram codec x1 x2 x32i x32o vddx4 gndx5 hold\ holda\ nmi\ int1\ rst\ ipt(7:0) opt(18:0) bio(7:0) xf\ data bus fllen\
4 mx93011a mx93011a 3.0 pin configuration 100 pqfp ead9 ead10 ead11 ead12 ead13 ead14 gnd vdd ead15 nmi\ int1\ opt18 cdr0 opt17 cmck cfs cdx0 opt16 bio0 bio1 ed11 ed12 ed13 vdd gnd ed14 ed15 x1 x2 cas\ drd\ dwr\ ras\ popt15 popt14 rst\ erom popt13 opt12 opt11 opt10 opt9 opt8 opt7 opt6 opt5 opt4 opt3 opt2 opt1 opt0 x32i x32o xf\ ipt7 ipt6 ipt5 ipt4 ipt3 ipt2 ipt1 ipt0 vdd gnd bio7 bio6 bio5 bio4 bio3 bio2 ed10 ed9 ed8 ed7 ed6 ed5 ed4 ed3 ed2 ed1 gnd vdd ed0 hold\ holda\ edce\ epce\ erd\ ewr\ ead0 ead1 ead2 ead3 ead4 ead5 ead6 fllen\ gnd ead7 ead8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 mx93011a
5 mx93011a mx93011a 3.1 pin descriptions power/clock/control pins: symbol pin type pin number description vdd 23, 43, 69, 84 5v power source gnd 24, 44, 53, 70, 85 ground x1/vdd 88 32.256mhz crystal input/connect to vdd in single low x'tal mode x2/gnd 89 32.256mhz crystal output/connect to vdd in single low x'tal mode rst\ is 96 power-on reset . xf\ oa 14 external flag if upmodx=1. this pin can be directly written by one dsp instruction. default inactive (5v output). hold\ is 67 hold dsp clock down and release bus holda\ oa/z 66 ack to hold\ signal erom is 97 disable internal rom; use external rom only. nmi\ is 41 non maskable interrupt pin. int1\ is 40 interrupt pin x32o 13 32.768khz crystal output. x32i 12 32.768khz crystal input. fllen\ is 54 1: dual x'tal mode. 0: single low x'tal mode. memory interface pins : symbol pin type pin number description ead0-ead15 oa/z 61-55, 52-45, 42 dsp io/ram/rom external address bus. ead0-ead14 are for dram address. ed0-ed15 it/oa/zr 68, 71-83, 86-87 dsp io/ram/rom/dram external data bus. with soft latch feed back current is 250ua. edce\ oa/z 65 external data chip enable. epce\ oa/z 64 external program chip enable. erd\ oa/z 63 sram/rom/io external read. ewr\ oa/z 62 sram/rom/io external write. cas\ oa 90 dram column address select. ras\ oa 93 dram row address select. drd\ oa 91 dram read. dwr\ oa 92 dram write.
6 mx93011a mx93011a ipt : input port symbol pin type pin number description ipt4-ipt7 is 18-15 input port. ipt0-ipt3 ish 22-19 input port with internal pull high resister(r=30k ohm) cfs oa 35 codec frame sync, 8 khz. (9.6khz) output low in power down mode. cmck oa 36 codec master clock, 1.536 mhz. output low in power down mode. cdx0 oa 34 codec data transmit cdr0 is 38 codec data receive codec interface pins: symbol pin type pin number description opt : output port symbol pin type pin number description opt0-opt15 ob 11-1,100-98 output to pin, all output values are registered and may be read back when read by 'in' instruction. opt16-opt18 it/oa/zr 33,37,39 output to pin, when upmodx=1 95,94 bio : bi-direction i/o symbol pin type pin number description bio7-bio0 it/oa 25-32 input/output port when upmodx=1. direction is controlled by bio15-bio8, (see bior). note: it ttl level input is cmos level schmidt trigger input (hysteresis:2v~3v) ish cmos level schmidt trigger input with internal pull high resistor(~30k ohm) oa 8ma drive level output ob 16ma drive level output z high impedance state zr high impedance state with soft latch
7 mx93011a mx93011a pin number pin name upmodx=1 (non_up mode) pin name upmodx=0(up mode) 25~32 bio(7:0) input/output port hdb(7:0) host data bus 39 opt18 output port hilo high low data select 37 opt17 output port hrd\ host read 33 opt16 output port hwr\ host write 14 xf\ external flag ack\ acknowledge to host pin number pin name fllen\=1(dual x'tal) pin name fllen\=0(single x'tal) 88 x1 32.256mhz crystal input vdd power vdd 89 x2 32.256mhz crystal output gnd power ground 3.2 pin type summary : input : cmos level schmidt trigger input: ipt7~ipt4,cdr0,int1\.nmi\,fllen\,hold\,rst\,erom cmos level schmidt trigger input with internal pull high resister: ipt3~ipt0 output: 8ma drive level output: xf\,cdx0,cfs, cmck,ras\,cas\,drd\,dwr\ 8ma drive level output/ high impedance state ead15~ead0,holda\,epce\,edce\,erd\,ewr\ 16ma drive level output : opt15~opt0 bi-direction: ttl level input/8ma output /high impedance state bio7~bio0 ttl level input/8ma output/high impedance state/soft latch ed15~ed0 , opt18~opt16 note upmodx:up mode select bit in control register,"0" is its power on reset value. note fllen\:pin 54. 3.3 multiplex pins
8 mx93011a mx93011a 4.0 functional description 4.1 loop repeat or loop instruction is important in dsp operation. the mx93011a supports this function by implementing many instructions which are implictly repeated with the number stored in the rcr register. loop up to 8 instructions with specified number of times (can be variable) is also implemented with hardware. furthermore, flexible usage format is supported which makes the instruction more useful. 4.2 modular addressing modular addressing is by modular operation at the output of arau. to use modular addressing user must first store non-zero number m which is stored to the modr register. with this in effect, memory space beginning from k2 n to k2 n +m, where k is an integer greater than or equal to zero and 2 n is a power-of-two integer greater than m, will form a circular memory space. whenever boundary location, 0 or m, is addressed, the next ar content will be set/reset to m/0, independent of the instruction specification. set modr to 0 will deactivate modular addressing. for example, if modr is set to 23, circular memory spaces will start from 32k to 32k+23. any instruction can be indirectly addressed to 55, assuming that using ar1, with increasing operation, will make the next ar1 content to be reset to 32. likewise, if ar1 content is in decreasing operation and the content of ar1 is set to 0, then the next value of ar1 will be reset to 23. if normal addressing mode is desired, simply output a 0 into the modr registers. this instruction can help construct data ram into circular buffer or delay line, thereby eliminating the need of physical data movement in the buffer or delay. however, the pointer need to be kept in the data ram for easy access to the head/tail of this buffer/delay line. 4.3 auxiliary registers eight 16 bits auxiliary registers are allocated together with a 16-bit adder/subtractor. the results of adder/ subtractor always go through a modulator to get modular addressing before being stored to the auxiliary registers. the process provides an independent processor to do address calculation and update in parallel with main data path which performs the instruction execution. of course, ar registers can also be used as temporary registers and as another unsigned adder/subtractor. ar register modification of (0,1,2,ar0) on the fly is also included. 4.4 stack hardware contains 32 deep dedicated stack memories, which support deep hierarchy code. stack manipulation is transparent to firmware. 4.5 hold hardware hold is supported through pins hold\ and holda\. when hold\ is activated, the mx93011a will enter hold state after the present instruction cycle is completed(instructions inside loop and inherent repeat instruction cycles is considered one instruction cycle). at hold state, the mx93011a will release address and data bus to high impedence, stop executing instruction and output holda\. after hold\ is invalid the mx93011a will bring holda\ to high and resume normal operation.
9 mx93011a mx93011a 4.6 memory maps: external on chip ram external all external data ram program rom or ram (ext) program rom or ram (ext) 0h 07ffh 0800h ffffh 07ffh 8000h ffffh ffffh erom='0' erom='1' on chip rom 0h 0h pwdn fllen\ fll 21 48 4 32 32 pwdn 0 1 pwdn hssrc dsp core cmck (8 khz) cfs (1.536 mhz) to codec timer interrupt to dsp 0 1 0 1 0 1 32768 hz 32.256 mhz dsp clock 32 khz 4.7 clock/timer/powerdown high frequency clock(32.256mhz) required for dsp running with can be generated from x'tal oscillator directly or derived from fll (frequency locked loop) by enabling fllen\ pin. one dsp instruction cycle needs one and half high clock cycle, so the dsp instruction cycle time is 46.5 nano seconds. when pwdn bit in control register(i/o register 07) is set, high x'tal and fll will be disabled, the dsp running clock will switch to be low clock (32768 hz) to reduce operating power. when this pwdn bit is reset, dsp will keep on slow speed running for 62.5 mili second, then switch back to normal speed running. lsruns bit in control register will reflect the status of the dsp running speed. timer interrupt request is generated every one milli second or 1/1024 second depending on hssrc bit being set or reset. in power down mode, interrupt occurs every 1/32 second. hssrc bit must be reset prior to high x'tal shut down. in single low x'tal mode, clock from fll output is not prescise enough to be used as timer base. choosing low clock directly from low x'tal output is better.(hssrc="0")
10 mx93011a mx93011a 4.8 addressing modes immediate constant immediate constant is coded directly in opcode. direct memory addressing dpr and iopr are used to completely specify addressing spaces. 4 bits in dpr combined with 7-bits coded in opcode, make direct memory address. (direct memory addressing only for internal 2k words ram) indirect addressing the memory address may be pointed by ars. ars also has post-addressing execution which provides powerful increment(s)/decrement(s) and modular indexing. it takes only 7 bits to code all these into one opcode to enable program size compact. see ar, arau and modr for more details. miscellaneous addressing mode call--call subroutine at the second word of call instruction. cala--acch indirect call, acch=called address bacc-- acch indirect branch, acch=branch address trap-- always call to hex 000c address
11 mx93011a mx93011a 4.9 interrupt : operations the interrupt source, vectoring address and priority are as follows: name vectored address descriptions rst\ 0000 power-on reset (top priority) nmi\ 0002 nmi\non.maskable interrupt, edge-triggered (high to low) ss 0004 single-step, single step interrupt is for debugging purpose. if set, the mx93011a will be interrupted after every instruction cycle (instructions inside loop and inherent repeat instruction cycles is considered as one instruction cycle). user can put debugging service as the interrupt service routine. int1\ 0006 int1\ pin interrupt, edge trigged codec 0008 triggered when codec registers get/send 16 bit data (see timing diagram) stmr 000a triggered by every 1/1024 second or 1milli second depend on the value of hssrc in normal running, but triggered by 1/32 second in power down mode. trap 000c triggered when executes trap interrupt process: (execute by hardware) 1. release related isr pending flag 2. push ssr onto stack 3. push return-address onto stack 4. disable global interrupt (same to excuting dint instruction) 5. if it is in software hold state ( see wstr register and power management), reset swhold ? 0, and come out of software hold state. issues of reti instruction: (execute by hardware) 1. pop return address to pc 2. pop ssr note that acc normally need to be saved. all other registers should also be carefully maintained when doing an in-and-out interrupt.
12 mx93011a mx93011a name bit ctlr io address related instructions descriptions optr 16 o 0 in/out output register iptr 8 o 1 in input port register bior 16 o 2 in/out bidirectional io register svr 4 3 in/out/sfr/sfl shifter count (scr) and sign imr 4 4 in/out interrupt mask register isr 3 5 in interrupt status register ctlr 15 7 in/out control register wstr 8 8 in/out wait state register rcr 7 12 in/rpt/lup repeat counter modr 7 13 in/mod modulo register spr 4 15 psh/pop/in/pshh/poph stack pointer register pshl,popl cdrr0 16 o 16 in codec 0 receive buffer cdxr0 16 o 17 out codec 0 transmit buffer acch 16 C (many instr.) upper word of dsp accumulator accl 16 C sal/adl/sbl lower word of dsp accumulator ar0-7 16x8 C lar/mar/sar for indirect memory access basically; also used in macro instructions accx 32 C sbl, adl, sfl sfr,multiply acch+accl=accx ssr 16 sss/out/bs/bz status register intm : eint/dint tb : bit ovm : rovm/sovm arp : mar pc 16 C call, cala, trap, bs, bz program counter bacc, ret, reti, interrupt, hardware reset 5.0 registers summary
13 mx93011a mx93011a 5.1 table of io mapped registers and its power on values optr:(00) rw iptr:(01) ro fe d cba 9 7 8 6 4 53 2 1 0 o opt15 o opt13 o opt12 o opt10 o opt11 o opt8 o opt9 o opt6 o opt7 o opt5 o opt4 o opt3 o opt2 o opt1 o opt0 cdrr0:(16) bior:(02) rw 0 bior14 0 opt13 0 bior13 0 bior10 0 bior11 0 bior8 0 bior9 0 bior6 0 bior7 0 bior5 0 bior4 0 bior3 0 bior1 0 bior0 x ipt0 x ipt1 x ipt2 x ipt3 x ipt4 x ipt5 x ipt6 x ipt7 svr:(03) rw 0 0 scr3~scr0 0 0 imr:(04) rw 1 ssm 1 codcm 1 intim isr:(05) ro 0 codcs 0 intis ctlr:(07) rw o opt18 o opt17 o opt16 0 swhold 0 pwdn 0 cmdrdy 0 hmod 0 lsruns 0 ss 0 hssrc 0 snsel 0 upmodx o cfssel wstr:(08) rw 0 1 rom wait 11 1 mm wait 11 1 mm size rcr:(12) ro 0000 0 0 0 modr:(13) ro 0000 0 0 0 spr:(15) ro 0000 0 ro x x xx x x x x xx xx xx x x cdxr0:(17) wo x x xx x x x x xx xx xx x x 1 sram wait 11 0 bior2 0 bior15 o opt14 0 stmrs 1 stmrm mmac:(09) rw rw mmaph:(11) rw toiram 0 0 0 00 0 00 0 0 ira(intermal ram address, brank one, 10 bits) 0 0 0 0 0 0 mmcnt (mass memory move count, 6 bits) mmapl:(10)
14 mx93011a mx93011a io registers 6.1 optr : output register (mapped to io register 00) 6.0 register description f e d c b a 9 8 7 6 5 4 3 2 1 0 rw opt15 opt0 output register (optr:15 ~ optr:0) 16 bit, connect to opt15~opt0 pins. positive logic, '1' will output 5 volt on output pin. ('0' for 0 v) rw f edcba987654321 0 bior15 bior8 bior7 bior0 when up modx=1, used for bidirectional io register. programable bidirectional io. bior15~bior8 control i/o direction of bior7~bior0, respectively (bit 8 control bit 0) bior7~bior0 connect to bio7~bio0 pins, respectively. bior6 bior5 bior4 bior3 bior2 bior1 bior9 bior10 bior11 bior12 bior13 bior14 6.3 bior/cmdr : bi-direction io register (mapped to io register 02) 6.2 ipt : input port register (mapped io address 01) f e d c b a 9 8 7 6 5 4 3 2 1 0 ro ipt7 ipt0 input port (ipt:7~ipt:0) positive logic, 5 volt input will read '1' (0v for '0') ipt:7~ipt:0 connect ipt7~ipt0 pins. ipt4 ipt5 ipt6 ipt3 ipt2 ipt1
15 mx93011a mx93011a 6.4 svr : shift variable register (mapped to io register 03) svr includes shift-count register (scr) note 1: codec tx/rx use this same mask. this is because the 2 events are synchronized and always happen at the same time. programmers should take care of these 2 events (if necessary) in this interrupt. note 2: isr:2~0 will reflect interrupt pending status on imr:2~0. note that single-step (ctlr:ss, register 07) is directly controlled by the program; no status exists. note 3: read isr will read and clear all pending flags. int1m - int1 \ interrupt mask 1 stmrm - system tick timer interrupt mask codcm - codec interrupt mask ssm - single step interrupt mask 6.6 isr : interrupt status register (mapped to io register 05) 6.5 imr : interrupt mask register (mapped to io register 04) f ed cb a9 87 6 54 3 21 0 1111 rw ssm stmrm codcm int1m f edcba9876543 210 00 00 rw scr3~scr0 when sfl/sfr instruction gives 0 as shift count, dsp uses the scr default count as shifting count. this mechanism provides run-time assigned shifting value. f edcba9 876 543210 0 0 0 ro codcs int1s stmrs
16 mx93011a mx93011a 6.7 ctlr : control register (mapped to io register 07) 6.8 wstr: wait state, and dram size register (mapped to io register 08) mass memory size : select dram configuration 00 -- x1 01 -- x4 10 -- x8 11 -- x16 wait state : choose apporiate wait_state number to meet the following requirement. 1.ram/rom(sram wait,rom wait) taa or tcs < 31 ns * (1.5 + wait_state) -20ns 2.dram(mm wait) trac < 15.5ns * (6 + wait_state) -20ns........(1) tcac < 15.5ns * (2+wait_state)-20ns .........(2) choose the larger wait_state in (1) and (2) as mm wait note: taa is the address access time. tcs is the chip select access time. trac is the access time from ras\. tcac is the access time from cas\. f e d c b a 9 8 7 6 5 4 3 2 1 0 rw 0 1 1 1 1 1 1 1 1 1 1 mmsize sramwait mmwait romwait rw f edcba987654321 0 opt18 swhold hmod cfssel opt17 opt16 pwdn cmdrdy lsruns ss hssrc upmodx snsel 1: select 9.6 khz codec frame sync. 0: select 8 khz codec frame sync. 0: up mode. 1: non_up mode. 0: no sign extension 1: msbs sign extented in adl, adll, sbl and sbll instructions. 0: normal operation. 1: single step mode. a interrupt will occur at end of each instruction. cmdrdy is cleared by cmdr read. 1: external up writes a command to dsp. 0: no write operation. in non- m p mode, the statuses of opt18, opt17, opt16 will be reflected to philo\, phrdb\, phwr\ respectively. 1: output 5v to philo\, phrdb\ and phwrb\ pins in up mode. 0: output 0v to philo\, phrdb\ and phwrb\ pins in up mode. 1: dsp runs at 32768 hz until reset to 0 0: normal operation. 1: it works as external hardware hold\ pin except issued by instructions and cleared by interrupt. 0: normal operation. 1: dsp will hold after the current fetched instruction has been excuted. 0: dsp runs until external bus is accessed. 1: 32 khz clock is generated from hi- crystal or fll 0: 32768 hz clock is from low crystal it's a status bit. 0: dsp is running at high speed mode. 1: dsp clock is 32768 hz 0 0 0 0 0 0 0 0 0 0 0 0 0
17 mx93011a mx93011a 6.9 mmacr : mass memory access control register (mapped to io register 9) 6.10 mmapl : mass memory access pointer low register (mapped to io regsiter 10) 6.11 mmaph : mass memory access pointer high register (mapped to io register 11) writing (out) a non zero value into mmcnt (reg 9) will start data movement between external dram and internal data ram and hold dsp operation till mmcnt=0. the starting address of data ram and dram are pointed by ira (reg 9) and mmaph+mmapl (reg 10 and 11). data movement will stop when dram address reach mmaph+mmapl+mmcnt. total data words being moved depend on what the dram configuration is. only data in ram bank 1 can be moved around. the direction of movement is decided by toiram(reg 11). toiram=1, dram --> internal ram toiram=0, dram<-- internal ram total 30 bits of mmaph+mmapl can address up to 1 giga dram space. f e d c b a 9 8 7 6 5 4 3 2 1 0 rw f e d c b a 9 8 7 6 5 4 3 2 1 0 rw toiram rw f edcba987654 3 2 1 0 0 00 00 000 00 0000 0 0 ira (internal ram address, bank one, 10 bits) mmcnt(mass memory move count, 6 bits)
18 mx93011a mx93011a ? rcr provides repeat count on, lup ? rcr must be prepared before macro instructions are being executed. (rpt instruction) ? repeat time is rcr+1 6.12 rcr : repeat counter register (mapped to io register 12) as modr=m ? 0, 1, 2, .., m-1, m modulo mechanism will be enforced (note: bounded by m --- not m-1) modular addressing is always performed at the output of arau. as modr=0, modulo addressing is disabled. mod type instructions are used to load modr; use in instruction to read modr. 6.13 modr : modular register (mapped to io register 13) 6.14 spr : stack pointer register (mapped to io register 15) 6.15 cdrr 0: codec data receive register (mapped to io register 16) f ed cb a9 87 6 54 3 21 0 ro oo o o o o o f ed cb a9 87 6 54 3 21 0 ro oo o o o ? 32-level stack provides nestable interrupt and controller level nested call capabilities. ? spr is pointing to 'next-available' word, and initialized to 0. ? as spr is over address 31, it wraps around to 0. as spr=0, pop will also wrap spr to 31. ? spr can only be read by in instructions; no write capability. f ed cb a9 87 6 54 3 21 0 ro oo o o o o o f ed cb a9 87 6 54 3 21 0 ro
19 mx93011a mx93011a 6.16 cdxr 0: codec data transmit register (mapped to io register 17) 1. two codec events from the above registers are always synchronized, so there is only one codec interrupt for them. 2. these codecs are in 16-bit mechanism; however, 8-bit codec is also applicable. in 8-bit case, to tx, the data byte to be transmitted must be in bit15~bit8. the received data byte is at bit15~bit8 as read from receive register. 3. msb (most-significant-bit) is shifted first. 4. codec registers has shadow registers as buffer. 6.17 acc:accumulator ? acch+accl=acc ? logic alu operation is 16 bits and executed on acch. (accl is not affected) ? adl/sbl is 32-bit operation. (svr:snsel determine sign-extended) ? lac will put accl to 0 acch accl acc = acch + accl f ed cb a9 87 6 54 3 21 0 ro
20 mx93011a mx93011a 6.18 ssr : status register ssr includes 8 testable status/register bits (ssr:15~8), and 3 arp bits, 2 iop bits, 4 dp bits sgn and acz reflect status of acch. (can not be saved) ? 16x8 ar registers provide powerful indirect memory access. ? modulo addressing (modulo memory indexing) provides easy implementation of ring buffer or delay line. see modulo register (modr) for more details. ? arau provides +/ - (0, 1, 2, ar0) post execution after each addressing of ars. ? arau works in parallel with main alu. ? ars may be also used as scratch registers. ar0 ar1 ar2 ar3 ar4 ar5 ar6 ar7 arau auxiliary registers auxiliary alu 16-bit register 6.19 ar (auxiliary register) and arau (auxiliary alu) ro rw ro rw ro rw rw ro rw this bit has two functions. it provides an "always true" condition for effectively unconditional branch (jump). it's also treat as "intm", global interrupt mask status. it can be only set 1 reset by eint and dint if intm=1, interrupt is prohibited. sign flag reflect acch directly, read-only acc zero flag this bit reflects acch current status directly. so, it is read only. overflow mode enable, used for overflow protection during +/ -/shift operations. arz registering the last operated ar=0 overflow flag for the last acch operation test bit, the tested memory bit is moved to tb register (bit instructions) a conditional test is normally followed but not necessary current active ar register pointer.. there are 8 16-bit ar registers in dspc. arz sgn ov acz tb ovm arp2~arp0 testable wo 1/intm iopr define 4 pages, 8 address in each page of io space 4-bit data page pointer defines 16 pages, 128 address in each page, of internal ram ovm iopr4~3 dpr3~dpr0
21 mx93011a mx93011a 6.20 pc and program flow control pc program counter program flow is affected by: 1. bs/bz (branch-if-set/branch-if-zero) conditional branch. 2. bacc - branch indirectly by acch. 3. cala - call indirectly by acch, return address is pushed. 4. call - call subroutine, see 'addressing modes, misc. addressing mode' 5. trap - trapped to call fixed hex 000c address. 6. power-on reset and interrupt see 'interrupt operations'
22 mx93011a mx93011a 7.0 instruction set summary abbreviations a : ar pointer ar : ar acc : accumulator c : short constant d : data memory address dp : data page pointer i : addressing mode select bit k : odd/even address select i : loop counter l : constant for shift left mr : modulo register o : io page pointer pa : port address pc : program counter r : constant for shift right rc : repeat counter s : shift right sign extention select bit sp : stack pointer ss : status register sv : shift register v : ar arithemetic operation selection x : don't care y : next ar arithmetic register selection mnemonic and description words & cycles 16-bit opcode msb lsb abs ; absolute value of accumulator 1,1 1001 1000 0xxx xxxx adh ; add to high acc 1.1 0000 0000 iddd dddd adhk ; add to high acc. short immediate 1,1 0000 0001 0ccc cccc adhl ; add to high acc. immediate 2,2 1000 0000 0xxx xxxx adl ; add to low acc 1,1 0000 0010 iddd dddd adlk ; add to low acc. short immediate 1,1 0000 0011 0xxx xxxx adll ; add to low acc. immediate 2,2 1000 0001 0xxx xxxx and ; and with high acc 1,1 0000 1010 iddd dddd andk ; and short immediate with high acc 1,1 0000 1011 0ccc cccc andl ; and immediate with high acc 2,2 1000 0101 0xxx xxxx bacc ; branch to address specified by acc 1,2 1111 1010 0xxx xxxx bit ; test bit 1,1 0110 bbbb iddd dddd
23 mx93011a mx93011a mnemonic and description words & cycles 16-bit opcode msb lsb bs ; branch immediate if bit set 2,3 1101 1bbb 0xxx xxxx bz ; branch immediate if bit reset 2,3 1101 0bbb 0xxx xxxx cala ; call subroutine indirect specified by acc 1,2 1100 0000 0xxx xxxx call ; call subroutine 2,3 1111 1100 0000 0000 dint ; disable interrupt 1,1 1111 0000 0xxx xxxx eint ; enable interrupt 1,1 1111 0001 0xxx xxxx in ; input data from port 1,1 1010 ppp0 iddd dddd lac ; load acc 1,1 0000 1110 iddd dddd lack ; load acc. short immediate 1,1 0000 1111 0ccc cccc lacl ; load acc. immediate 2,2 1000 0111 0xxx xxxx lar ; load auxiliary register 1,1 0111 aaa0 iddd dddd lark ; load auxiliary register short immediate 1,1 0111 aaa1 0ccc cccc larl ; load auxiliary register immediate 2,2 1000 1000 0aaa 0000 ldp ; load data page register 1,1 0001 0100 iddd dddd ldpk ; load short immediate to data page 1,1 0001 0101 0xxx cccc register lip ; load io page register 1,1 0001 0010 iddd dddd lipk ; load io page register with short 1,1 0001 0011 0xxo oxxx immediate lup ; loop instruction 1,1 0101 lll0 iddd dddd lupk ; load rc with 7-bit constant and enable 1,1 0101 lll1 0ccc cccc loop operation mar ; modify auxiliary register 1,1 1111 0110 1ddd dddd mod ; load modulo register 1,1 0001 0110 iddd dddd modk ; load modulo register short immediate 1,1 0001 0111 0ccc cccc nop ; no operation 1,1 1111 1111 1111 1111 or ; or with high acc 1,1 0000 1000 iddd dddd ork ; or short immediate with high acc 1,1 0000 1001 0ccc cccc orl ; or immediate with high acc 2,2 1000 0100 0xxx xxxx out ; output data to port 1,1 0100 ppp0 iddd dddd outk ; output short immediate to port 1,1 0100 ppp1 0ccc cccc outl ; output immediate to port 2,2 1000 1111 0ppp 0000 pop ; pop top of stack to data memory 1,1 1011 0101 iddd dddd poph ; pop top of stack to high accumulator 1,1 1001 0100 0xxx xxxx popl ; pop top of stack to low accumulator 1,1 1001 1011 0xxx xxxx psh ; push data memory value onto stack 1,1 1100 1010 iddd dddd pshh ; push high accumulator onto stack 1,1 1100 1000 1vvv vvvv pshl ; push low accumulator onto stack 1,1 1100 1001 1vvv vvvv ret ; return from subroutine 1,2 1111 1000 0xxx xxxx reti ; return from interrupt 1,2 1111 1001 0xxx xxxx rpt ; load repeat counter 1,1 0001 0000 iddd dddd rptk ; load rc with 7-bit constant 1,1 0001 0001 0ccc cccc rxf ; reset external flag 1,1 1111 0010 0xxx xxxx
24 mx93011a mx93011a mnemonic and description words & cycles 16-bit opcode msb lsb sah ; store high acc. 1,1 1011 0000 iddd dddd sal ; store low acc 1,1 1011 0001 iddd dddd sar ; store auxiliary register 1,1 1011 1aaa iddd dddd sbh ; subtract from high acc 1,1 0000 0100 iddd dddd sbhk ; subtract short immediate from high acc1,1 0000 0101 0ccc cccc sbhl ; subtract immediate from high acc 2,2 1000 0010 0xxx xxxx sbl ; subtract from low acc 2, 2 0000 0110 iddd dddd sblk ; subtract short immediate from low acc 1,1 0000 0111 0ccc cccc sbll ; subtract immediate from low acc 1,1 1000 0011 0xxx xxxx sdp ; store datapage register 1,1 1011 0100 iddd dddd sfl ; shift acc left 1,1 1001 1101 0000 llll sfr/sfrs ; shift acc right 1,1 1001 1110 000s rrrr sip ; store iopage register 1,1 1011 0010 iddd dddd sss ; store ss register 1,1 1011 0011 iddd dddd sxf ; set external flag 1,1 1111 0011 0xxx xxxx trap ; software interrupt 1,2 1100 0010 0xxx xxxx xor ; xor with high acc 1,1 0000 1100 iddd dddd xork ; xor short immediate with high acc 1,1 0000 1101 0ccc cccc xorl ; xor immediate with high acc 2,2 1000 0110 0xxx xxxx
25 mx93011a mx93011a abs absolute value of accumulator. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 10011 0000 syntax: abs execution: (pc) + 1 ? pc |acc(31:16)| ? (acc (31:16)) words: 1 cycles: 1 adh add to high acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 1 see note 1 syntax: adh dma7 adh *(,nar) execution: (pc) + 1 ? pc (acc(31:16))+(dma) ? (acc (31:16)) words: 1 cycles: 1(di) 2(de) adhk add to high acc. short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 7-bit constant syntax: adhk cnst 7 execution: (pc) + 1 ? pc (acc(31:16)) + (7-bit constant) ? (acc (31:16)) words: 1 cycles: 1 8.0 instruction set description
26 mx93011a mx93011a adhl add to high acc. immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100000000 16-bit constant syntax: adhl cnst16 execution: (pc) + 2 ? pc (acc(31:16))+(16-bit constant) ? (acc (31:16)) words: 2 cycles: 2 adl add to low acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 1 see note 1 syntax: adl dma7 adl *(,nar) execution: (pc) + 1 ? pc (acc)+(dma with optional msbs sign extension) ? (acc) words: 1 cycles: 1(di) 2(de) note: option is controlled by ctrl: snsel bit
27 mx93011a mx93011a adlk add to low acc. short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 0 7-bit constant syntax: adlk cnst7 execution: (pc) + 1 ? pc (acc)+(7-bit constant) ? (acc) words: 1 cycles: 1 adll add to low acc. immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100000010 16-bit constant syntax: adll cnst16 execution: (pc) + 2 ? pc (acc)+(16-bit constant with optional msbs sign extension*) ? (acc) words: 2 cycles: 2 note:option is controlled by ctrl :sense bit
28 mx93011a mx93011a and and with high acc. direct: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 0 1 0 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 0 1 0 1 0 1 see note 1 syntax: and dma7 and *(,nar) execution: (pc) + 1 ? pc (acc(31:16)) .and. (dma) ? (acc(31:16)) words: 1 cycles: 1(di) 2(de) andk and short immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 0 0 0 0 1 0 1 1 0 7-bit constant syntax: andk cnst7 execution: (pc) + 1 ? pc (acc(23:16) .and. (7-bit constant) ? (acc(23:16)) 0 ? acc(31:24) words: 1 cycles: 1
29 mx93011a mx93011a andl and immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 543210 100001010 16-bit constnat syntax: andl cnst16 execution: (pc) + 2 ? pc (acc(31:16)) .and. (16-bit constant) ? (acc(31:16)) words: 2 cycles: 2 bacc branch to address specified by acc. bit: 15 14 13 12 11 10 9 8 7 6 543210 111110100 syntax: bacc execution: (acc (31:16)) ? pc words: 1 cycles: 2
30 mx93011a mx93011a bit test bit. direct: 15 14 13 12 11 10 9 8 7 6 543210 0 1 1 0 bbbb 0 data memory address indirect 15 14 13 12 11 10 9 8 7 6 543210 0 1 1 0 bbbb 1 see note 1 syntax: bit dma7, bbbb bit *,bbbb (,nar) execution: (pc) + 1 ? pc (dma) ? ss(tb) words: 1 cycles: 1(di) 2(de) bs branch immediate if bit set. bit: 15 14 13 12 11 10 9 8 7 6 543210 11011 bbb 0 program memory address syntax: bbb, pma16 execution: if ss(#1bbb)=1 then (pma) ? pc else (pc)+2 ? pc words: 2 cycles: 3
31 mx93011a mx93011a bz branch immediate if bit reset. bit: 15 14 13 12 11 10 9 8 7 6 543210 11010 bbb 0 program memory address syntax: bz bbb, pma16 execution: if ss(#1bbb)=0 then (pma) ? pc else (pc)+2 ? pc words: 2 cycles: 3 cala call subroutine indirect. bit: 15 14 13 12 11 10 9 8 7 6 543210 110000000 syntax: cala execution: (pc)+1 ? (sp) (acc(31:16)) ? pc words: 1 cycles: 2
32 mx93011a mx93011a call subroutine . bit: 15 14 13 12 11 10 9 8 7 6 543210 1111110000000000 16-bit constant syntax: call pma16 execution: (pc)+1 ? (sp) (16-bit constant) ? pc words: 2 cycles: 3 dint disable interrupt. bit: 15 14 13 12 11 10 9 8 7 6 543210 111100000 syntax: dint execution: (pc) + 1 ? pc 1 ? (intm) status bit words: 1 cycles: 1
33 mx93011a mx93011a eint enable interrupt. bit: 15 14 13 12 11 10 9 8 7 6 543210 111100010 syntax: eint execution: (pc) + 1 ? pc 0 ? (intm) status bit words: 1 cycles: 1 in input data from port. direct: 15 14 13 12 11 10 9 8 7 6 543210 1010 port address 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 543210 1010 port address 0 1 see note 1 syntax: in dma7,port in *,port(,nar) execution: (pc) + 1 ? pc port address ? a2-a0 (iopr(4:3)) ? a4-a3 0 ? a15-a6 (ior) ? dma words: 1 cycles: 1; note:only for internal memory
34 mx93011a mx93011a lack load acc. short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 0 0 0 0 1 1 1 1 0 7-bit sonstant syntax: lack cnst7 execution: (pc) + 1 ? pc (7-bit constant) ? acc(23:16) 0 ? acc(31:24) 0 ? acc(15:0) words: 1 cycles: 1 lacl load acc. immediate bit: 15 14 13 12 11 10 9 8 7 6 5 43210 100001110 16-bit constant syntax: lacl cnst16 execution: (pc) + 2 ? pc (16-bit constant) ? acc(31:16) 0 ? acc(15:0) words: 2 cycles: 2 lac load acc. direct: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 0 1 1 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 0 1 1 1 0 1 see note 1 syntax: lac dma7 lac *(,nar) execution: (pc) + 1 ? pc (dma) ? acc(31:16) 0 ? acc(15:0) words: 1 cycles: 1(di) 2(de)
35 mx93011a mx93011a lark load auxiliary register short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 0 1 1 1 arp 1 0 7-bit constant syntax: lark cnst7, arp execution: (pc) + 1 ? pc (7-bit constant) ? (ar(6:0)) 0 ? ar(15:7) words: 1 cycles: 1 lar load auxiliary register. direct: 15 14 13 12 11 10 9 8 7 6 543210 0 1 1 1 arp 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 543210 0 1 1 1 arp 0 1 see note 1 syntax: lar dma7, arp lar *,arp(,nar) execution: (pc) + 1 ? pc (dma) ? (ar) words: 1 cycles: 1(di) 2(de) ; no manipulation on ars
36 mx93011a mx93011a larl load auxiliary register immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 100010000 arp 0000 1514131211109876543210 16-bit constant syntax: larl cnst16, arp execution: (pc) + 2 ? pc (16-bit constant) ? ar (15:0) words: 2 cycles: 2 ldp load data-page register. direct: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 1 0 1 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 543210 0 0 0 1 0 1 0 0 1 see note 1 syntax: ldp dma7 ldp *(,nar) execution: (pc) + 1 ? pc (dma(3:0)) ? (dp(3:0)) words: 1 cycles: 1(di) 2(de) ldpk load short immediate to data page register. bit: 15 14 13 12 11 10 9 8 7 6 5 43210 0 0 0 1 0 1 0 1 0 x x x 4-bit constant syntax: ldpk cnst4 execution: (pc) + 1 ? pc (4-bit constant) ? (dp(3:0)) words: 1 cycles: 1
37 mx93011a mx93011a lipk load io page register with short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000100110xxs1s0xxx syntax: lipk cnst2 execution: (pc) + 1 ? pc s1 ? iop(1), s0 ? iop(0) words: 1 cycles: 1 lip load io page register direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 1 see note 1 syntax: lip dma7 lip *(,nar) execution: (pc) + 1 ? pc (dma) ? (iop(1:0)) words: 1 cycles: 1(di) 2(de)
38 mx93011a mx93011a lup loop instruction. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0101 loop number 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0101 loop number 0 1 see note 1 syntax: lup dma, lic lup *,lic(,nar) execution: (pc) + 1 ? pc (dma) ? (rc) (loop number) ? (loop counter) words: 1 cycles: 1(di) 2(de); the next (loop number+1) words will be repeat (rc+1) times lupk load rc with 7-bit constant and enable loop operation. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0101 loop number 1 0 7-bit constant syntax: lupk cnst7, lic execution: (pc) + 1 ? pc (7-bit constant) ? (rc) (loop number) ? (loop counter) words: 1 cycles: 1
39 mx93011a mx93011a modk load modulo register short immediate. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 1 0 7-bit constant syntax: modk cnst7 execution: (pc) + 1 ? pc (7-bit constant) ? mr(6:0) words: 1 cycles: 1 mod load modulo register. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 0 data memory address indirect 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 0 1 see note 1 syntax: mod dma7 mod *(,nar) execution: (pc) + 1 ? pc (dma(6:0)) ? mr(6:0) words: 1 cycles: 1(di) 2(de) mar modify auxiliary register. indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 1 see note 1 syntax: mar *(,nar) execution: (pc) + 1 ? pc modifies arp, ar(arp) as specified by the indirect addressing field words: 1 cycles: 1
40 mx93011a mx93011a nop no operation. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1111111111111111 syntax: nop execution: (pc) + 1 ? pc words: 1 cycles: 1 or or with high acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 1 see note 1 syntax: or dma7 or *(,nar) execution: (pc) + 1 ? pc (acc(31:16)).or. (dma) ? (acc(31:16)) words: 1 cycles: 1(di) 2(de)
41 mx93011a mx93011a ork or short immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 1 0 7-bit constant syntax: ork cnst7 execution: (pc) + 1 ? pc (acc(23:16) ).or. (7-bit constant) ? (acc(23:16) (acc(31:24)) ? acc(31:24) words: 1 cycles: 1 orl or immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100001000 16-bit constant syntax: orl cnst16 execution: (pc) + 2 ? pc (acc(31:16)) .or. (16-bit constant) ? (acc(31:16) words: 2 cycles: 2
42 mx93011a mx93011a out output data to port. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0100 port address 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0100 port address 0 1 see note 1 syntax: out dma7, port out port *(,nar) execution: (pc) + 1 ? pc (pa) ? address bus a1-a0 (iopr)(4:3) ? a4-a0 0 ? a15-a5 words: 1 cycles: 1;note: for internal memory only outk output short immediate to port. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0100 port address 1 0 7-bit constant syntax: outk cnst7, port execution: (pc) + 1 ? pc (pa) ? address bus a2-a0 (iopr)(4:3) ? a4-a3 0 ? a15-a5 (7-bit constant ) ? ior (addressed by a4-a0) words: 1 cycles: 1; note: for internal memory only
43 mx93011a mx93011a outl output immediate to port. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100011110 port address 0000 16-bit constant syntax: outl cnst16, port execution: (pc) + 1 ? pc (pa) ? address bus a2-a0 (iopr)(4:3) ? a4-a3 0 ? a15-a5 (16-bit constant) ? ior(addressed by a4-a0) words: 1 cycles: 1;note: for internal memory only poph pop top of stack to high accumulator. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100101000 syntax: poph execution: (pc) + 1 ? pc (tos) ? acc(31:16) words: 1 cycles: 1
44 mx93011a mx93011a popl pop top of stack to low accumulator. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100110110 syntax: popl execution: (pc) + 1 ? pc (tos) ? acc(15:0) words: 1 cycles: 1 pop pop top of stack to data memory. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 1 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 1 1 see note 1 syntax: pop dma pop *(,nar) execution: (pc) + 1 ? pc (tos) ? dma words: 1 cycles: 1(di) 2(de)
45 mx93011a mx93011a psh push data memory value onto stack. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 1 0 1 see note 1 syntax: psh dma psh *(,nar) execution: (pc) + 1 ? pc dma ? (tos) words: 1 cycles: 1 pshh push high accumulator onto stack. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 0 1 see note 1 syntax: pshh execution: (pc) + 1 ? pc acc(31:16) ? (tos) words: 1 cycles: 1
46 mx93011a mx93011a pshl push low accumulator onto stack. bits: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 0 0 1 0 0 1 1 see note 1 syntax: pshl execution: (pc) + 1 ? pc acc(15:0) ? (tos) words: 1 cycles: 1 ret return from subroutine. bits: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 111110000 syntax: ret execution: (sp) ? pc sp-1 ? sp words: 1 cycles: 2
47 mx93011a mx93011a rptk load rc with 7-bit constant. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 1 0 7-bit constant syntax: rptk cnst7 execution: (pc) + 1 ? pc (7-bit constant) ? (rc) words: 1 cycles: 1 reti return from interrupt. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 111110010 syntax: reti execution: (sp) ? pc (sp)-1 ? sp (sp) ? ss sp-1 ? sp words: 1 cycles: 2 rpt load repeat counter. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 000100000 data memory address ` indirect:l 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 0 0 0 0 1 see note1 syntax: rpt dma 7 rpt *(,nar) execution: (pc) + 1 ? pc (dma) ? (rc) words: 1 cycles: 1(di) 2(de)
48 mx93011a mx93011a rxf reset external flag. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 111100100 syntax: rxf execution: (pc) + 1 ? pc 0 ? (xf) pin and status bit. words: 1 cycles: 1 sah store high acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 0 1 see note 1 syntax: sah dma7 sah *(,nar) execution: (pc) + 1 ? pc (acc(31:16)) ? (dma) words: 1 cycles: 1(di) 2(de)
49 mx93011a mx93011a sal store low acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 1 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 0 1 1 see note 1 syntax: sal dma7 sal *(,nar) execution: (pc) + 1 ? pc (acc(15:0)) ? (dma) words: 1 cycles: 1(di) 2(de) sar store auxiliary register. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 ar 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 1 ar 1 see note 1 syntax: sar dma7, arp sar *, arp (,nar) execution: (pc)+1 ? pc (ar) ? (dma) words: 1 cycles: 1(di) 2(de)
50 mx93011a mx93011a sbh subtract from high acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 1 see note 1 syntax: sbh dma7 sbh *(,nar) execution: (pc) +1 ? pc (acc(31:16)) - (dma) ? (acc(31:16)) words: 1 cycles: 1(di) 2(de) sbhk subtract short immediate from high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 1 0 7-bit constant syntax: sbhk cnst7 execution: (pc)+1 ? pc (acc(31:16)) - (7-bit constant) ? (acc(31:16)) words: 1 cycles: 1
51 mx93011a mx93011a sbhl subtract immediate from high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100000100 16-bit constant syntax: sbhl cnst16 execution: (pc)+2 ? pc (acc(31:16)) - (16-bit constant) ? (acc(31:16)) words: 2 cycles: 2 sbl subtract from low acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 0 1 see note 1 syntax: sbl dma7 sbl *(,nar) execution: (pc)+1 ? pc (acc) - (dma with optional msbs sign extension*) ? (acc) words: 1 cycles: 1(di) 2(de) ; note : option is controlled by ctrl : sense bit
52 mx93011a mx93011a sblk subtract short immediate from low acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 1 0 7-bit constant syntax: sblk cnst7 execution: (pc)+1 ? pc (acc) - (7-bit constant) ? (acc) words: 1 cycles: 1 sbll subtract immediate from low acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100000110 16-bit constant syntax: sbll cnst16 execution: (pc)+2 ? pc (acc) - (16-bit constant with optional msbs sign extension*) ? (acc) words: 2 cycles: 2 ; note:option is controlled by ctrl: sense bit
53 mx93011a mx93011a sfl shift acc left. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 0 1 0 0 0 0 shift syntax: sfl cnst4 execution: (pc)+1 ? pc if (shift>< 0) then acc * (2** shift) ? acc else acc*(2**(sv(3:0))) ? acc words: 1 cycles: 1 ; note sdp store data_page register. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 1 0 0 1 see note 1 syntax: sdp dma7 sdp *(,nar) execution: (pc)+1 ? pc (dp) ? (dma) words: 1 cycles: 1(di) 2(de)
54 mx93011a mx93011a sfr/sfrs shift acc right. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 1 1 1 1 0 0 0 0 s shift syntax: sfr cnst4 sfrs cnst4 execution: (pc)+1 ? pc if (shift>< 0) then acc * (2**( -shift)) ? acc else acc*(2**(-sv(3:0)) ? acc * s=0 the msbs zero-filled * s=1 the msbs sign-extended words: 1 cycles: 1 sip store io_page register direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 1 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 1 0 1 see note 1 syntax: sip dma7 sip *(,nar) execution: (pc)+1 ? pc iopr(4:3) ? (dma (1:0)) words: 1 cycles: 1(di) 2(de)
55 mx93011a mx93011a sss store ss register. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 1 1 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 1 1 0 0 1 1 1 see note 1 syntax: sss dma7 sss *(,nar) execution: (pc)+1 ? pc (ss) ? (dma) words: 1 cycles: 1(di) 2(de) sxf set external flag. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 111100110 syntax: sxf execution: (pc)+1 ? pc 1 ? (xf) pin and status bit. words: 1 cycles: 1
56 mx93011a mx93011a trap software interrupt. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 110000100 syntax: trap execution: (pc)+1 ? sp 0c ? pc words: 1 cycles: 2 xor xor with high acc. direct: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 0 data memory address indirect: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 1 see note 1 syntax: xor dma7 xor *(,nar) execution: (pc)+1 ? pc (acc(31:16)) .xor. (dma) ? (acc(31:16) words: 1 cycles: 1(di) 2(de)
57 mx93011a mx93011a xork xor short immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 0 7-bit constant syntax: xork cnst7 execution: (pc)+1 ? pc (acc(23:16)) .xor. (7-bit constant) ? (acc(23:16)) (acc(31:24)) ? acc(31:24) words: 1 cycles: 1 xorl xor short immediate with high acc. bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 100001100 16-bit constant syntax: xorl cnst16 execution: (pc)+2 ? pc (acc(31:16)) .xor. (16-bit constant) ? (acc(31:16)) words: 2 cycles: 2
58 mx93011a mx93011a * note 1 : 15 141312111098765432 10 opcode 1 vvvv y operation: case(vvvv) 0000: no manipulation of ars/arp 0001: y ? arp 0010: ar(arp) - ar0 ? ar(arp) 0011: ar(arp) - ar0 ? ar(arp), y ? arp 0100: ar(arp) + ar0 ? ar(arp) 0101: ar(arp) + ar0 ? ar(arp), y ? arp 1000: ar(arp) +1 ? ar(arp) 1001: ar(arp) +1 ? ar(arp), y ? arp 1010: ar(arp) - 1 ? ar(arp) 1011: ar(arp) -1 ? ar(arp), y ? arp 1100: ar(arp) +2 ? ar(arp) 1101: ar(arp) +2 ? ar(arp), y ? arp 1110: ar(arp) -2 ? ar(arp) 1111: ar(arp) -2 ? ar(arp), y ? arp operand: + 0 + 0 ,y - ar0 - ar0 + ar0 + ar0 + + , y - - , y ++ ++ , y -- -- , y
59 mx93011a mx93011a 9.0 dc characteristics: ta = 0 to 70 c, vcc = 5v 10% storage temperature range : -55 c - 150 c symbol parameter condition min type max unit vcc supply voltage 4.5 5 5.5 v gnd ground 0v ttl level input(it) vih input high voltage 2.0 v vil input low voltage 0.8 v schmitt trigger input(is) vih input high voltage 0.7*vcc v vil input low voltage 0.3*vcc v 8ma output(oa) voh output high voltage ioh=-8ma 2.4 v vol output low voltage iol= 8ma 0.4 v 16ma output(ob) voh output high voltage ioh=-16ma 2.4 v vol output low voltage iol=16ma 0.4 v supply cerrent icc normal 45 70 ma icc hold mode 10 ma icc power down 3 6 ma
60 mx93011a mx93011a 10.ac timing and characteristics: reset timing reset timing symbol parameter min nom max unit tw (rst) reset low pulse width 2*46.5ns output port and external flag(xf\) timing output ports and external flag (xf\) timing symbol parameter min nom max unit td (a-o) address to output ports delay time 0 10 ns ad15-ad0 ead15-ead0 opt18~opt0 bio7~bio0 xf\ pc=n, sxf/rxf or out xx pc=n+1 pc=n+2 td(a-o) rst\ ead15~ead0 ed15~ed0 control signals valid valid tw(rst) 0001 pc=0000 (inactive) 0000 opt18~opt0 bio7~bio0 note: control signals holda\edce\epce\erd\ewr\ cas\ras\drd\dwr\
61 mx93011a mx93011a codec transmit and receive timing symbol parameter min nom max unit tc cmck cycle time 650 ns tlpd cmck low pulse duration 315 335 ns thpd cmck high pulse duration 315 335 ns td (ch-fs) cmck to cfs delay time 20 ns td (ch-dx) cmck rising edge to dx valid 10 ns ts (dr) dr set-up time before cmck falling edge 10 ns th (dr) dr hold time before cmck falling edge 10 ns interrupt timing symbol parameter min nom max unit tw int\ low pulse duration 3q* ns n=1 n=2 n=3 n=4 sampling 16 bits n=1 n=2 n=3 n=4 transmit 16 bits td(ch-fs) td(ch-fs) ts(dr) th(dr) tc thpd tlpd td(ch-dx) cmck cfs cdr0 cdx0 int0\ int1\ int2\ ad15-ad0 tw fetch n+0 fetch n+1 fetch n+1 fetch n+1 fetch i note:q=15.5 ns
62 mx93011a mx93011a sram/rom read timing edce\,epce\ ead15-ead0 erd\ ed15-ed0 data in tcs taa tdr toh sram write timing *note : t=31ns w:wait state number symbol parameter min nom max unit tcs chip select access time 26.5+wxt ns taa address access time 26.5+wxt ns tdr data read setup time 12 ns toh data hold from end of read 0 ns tas address setup time 0 5 ns tdw data to ewr\ low overlap 12 ns tdh data hold from end of write 0 ns twr write recovery time 0 ns edce\ ead15-ead0 ewr\ ed15-ed0 tas tdw data out tdh twr
63 mx93011a mx93011a symbo parameter min nom max unit ts (a-h) address set-up time before hold\ low 5 3q-10 ns td (hh-ha) hold\ high to holda\ high 0 1q 1q+10 ns ten (ah-a) address driven after holda\ high 1q-10 1q 2q ns * note : q=15.5n cas\ before ras\ refresh timing symbo parameter min nom max unit t rp ras\ precharge time 77.5 ns t rpc ras\ to cas\ precharge time 62 ns t cp cas\ precharge time 31 ns t csr cas\ set-up time (cbr cycle) 15.5 ns t chr cas\ hold time (cbr cycle) 62 ns t ras ras\ pulse width 108.5 ns trpc trp tcp tcsr tras tchr trp ras\ cas\ hold timing n n+1 n+2 n+3 n+4 ts(a-h) ten(ah-a) td(hh-ha) ead15-ead0 ed15-ed0 epce\ edce\ ewr\ erd\ hold\ holda\
64 mx93011a mx93011a dram read/write timing symbo parameter min nom max unit trp ras\ precharge time 77.5 ns trcd ras\ to cas\ delay time 62 ns tcas cas\ low pulse duration 31+w*q ns tcp cas\ precharge time 31 ns tasr row address set-up time 0 ns trah row address hold time 31 ns tasc column address setup time 0 ns tach column address hold time 31 ns td(rd-c) drd\ low to cas\ low 0 ns td(wr-c) dwr\ low to cas\low 0 ns ts(cas) data set-up time before cas\ high 20 ns th(cas) data hold time after cas\high 0 ns ts(w-ca) data set-up time before cas\low 0 ns th(w-ca) data hold time after cas\low 46.5 ns row address column address column address data in data in data out trcd trp tasc tach tcas tcp tasr trah td(rd-c) ts(cas) th(cas) td(wr-c) ts(w-ca) th(w-ca) ras\ cas\ ead15-ead0 drd\ ed15-ed0 read cycle dwr\ ed15-ed0 write cycle *note: w:wait state number of dram q:15.5ns
65 mx93011a mx93011a 12.0 ordering information part no. package mx93011a pqfp mx 93 011a f c commercial 0 ~ 70 c mxic compony prefix family prefix package type f : pqfp product number
66 mx93011a mx93011a 13.0 package information 100-pin pqfp a b e cd i h g f 130 31 50 51 80 81 100 n m j k l p o item millimeters inches a 24.80 .40 .976 .016 b 20.00 .13 .787 .005 c 14.00 .13 .551 .005 d 18.80 .40 .740 .016 e 12.35 [ref] .486 [ref] f .83 [ref] .033 [ref] g .58 [ref] .023 [ref] h .30 [typ.] .012 [typ.] i .65 [typ.] .026 [typ.] j 2.40 [typ.] .094 [typ.] k 1.20 [typ.] .047 [typ.] l .15 [typ.] .006 [typ.] m .10 max. .004 max. n 2.75 .15 .108 .006 o .10 min. .004 min. p 3.30 max. .130 max. note: each lead centerline is located within .25mm[.01 inch] of its true position [tp] at a maximum material condition.
67 mx93011a mx93011a macronix international co., ltd headquarters : tel : +886-3-578-8888 fax : +886-3-578-8887 europe office : tel : +32-2-456-8020 fax : +32-2-456-8021 japan office : tel : +81-44-246-9100 fax : +81-44-246-9105 singapore office : tel : +65-747-2309 fax : +65-748-4090 taipei office : tel : +886-2-2509-3300 fax : +886-2-2509-2200 macronix america inc. tel : +1-408-453-8088 fax : +1-408-453-8488 chicago office : tel : +1-847-963-1900 fax : +1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.
mx93011a mx93011a mx93011a datasheet version 1.0 jul 5 ,1996

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